1. Field of the Invention
The present invention relates generally to an input apparatus for a multi-channel device, such as a logic analyzer, more particularly, to a time delay compensation circuit disposed within said input apparatus for compensating for variations in signal propagation time which inherently exists within the channels of said multi-channel device.
2. Description of the Prior Art
Most advanced electronic equipment in use today include complex integrated circuit logic systems, such as those used in microprocessors. Complicated multi-channel devices, such as a logic analyzer, are used for troubleshooting these logic systems. Most existing logic analyzers include a multi-channel probe input attached thereto, for example, a 16-channel probe, for acquiring logic signals, and a storage area (e.g., an acquisition memory) for storing the logic signals therein. The logic signals stored in the storage area are retrieved therefrom for display on the logic analyzer display. However, a large number of cables are used for connecting each probe to the logic analyzer. Usually, the length of any one cable is different than the length of any of the other adjacent cables. Since the logic signals must be transmitted through these cables, if a particular cable is longer than another adjacent cable, a longer period of time is required for the logic signal to be transmitted through the former cable than it is for the logic signal to be transmitted through the adjacent cable. Any difference in cable length, among these cables, results in skewed logic data signals displayed on the cathode ray tube (CRT) screen of the logic analyzer. These skewed data signals introduce a measurement error. Skewed logic data signals are also produced as a result of differences in propagation time delay through the input circuitry of the logic analyzer. This measurement error is not acceptable, especially when it occurs in conjunction with high-frequency, or high-acquisition rate test instruments.